Semiconductor integrated circuit device and manufacturing method thereof

ABSTRACT

A shielding film having a higher lead content than that of a capacitive insulating film is formed under a lower electrode of a capacitor in a FeRAM memory cell, and another shielding film having a higher lead content than that of the capacitive insulating film is formed on an upper electrode. PZT films to be used as barrier layers are formed in the interlayer insulating films of the FeRAM memory cell. As a result, it is possible to prevent H 2  or H 2 O from entering an upper portion or a lower portion of the capacitor, and lead diffused from the capacitive insulating film can be compensated by lead included in the shielding films, and it is possible to prevent characteristics of the capacitive insulating film from being degraded.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a semiconductor integratedcircuit device and a manufacturing technique therefor. Morespecifically, the present invention relates to a technique effectivelyapplicable to a FeRAM (Ferroelectric Random Access Memory).

[0002] A ferroelectric random access memory (FeRAM) is a nonvolatilememory using a binary characteristic of the polarization state of PZT(Pb(Zr_(y)Ti_(z))O₃) or the like which is a ferroelectric substance. Amemory cell of this FeRAM consists of one memory cell selection MISFETand one information capacitor. A PZT film is used as the capacitiveinsulating film of the capacitor.

[0003] Since the ferroelectric substance such as a PZT film containsmuch oxygen liable to cause reaction, the degraded by various treatmentsconducted in manufacturing steps.

[0004] For example, Japanese Patent Laid-open No. 8-55850 and No.10-321811 describe a technique for preventing a reaction with oxygen byforming a hydrogen barrier layer.

[0005] Japanese Patent Laid-open No. 10-163437 describes a technique forpreventing the reaction of oxygen contained in a capacitive insulatingfilm constituting a capacitive element by covering the upper surface ofthe capacitive element with a sacrificial protection film.

[0006] Japanese Patent Laid-open No. 11-135736 describes a technique forpreventing the degradation of a ferroelectric substance and ahigh-dielectric-constant material due to a reduction atmosphere bycovering an overall capacitive element with a hydrogen barrier film.

SUMMARY OF THE INVENTION

[0007] Inventors of the present invention have developed the capacitiveelement of an FeRAM. The polarization characteristic of thisferroelectric film is degraded by the presence of either H₂ (hydrogen)or H₂O (water).

[0008] One of the causes of the occurrence of either hydrogen or H₂O isthe presence of an interlayer insulating film. That is, in the formationof a silicon oxide film, a silicon nitride film or the like by a plasmaCVD (Chemical Vapor Deposition) method, hydrogen or H₂O is generatedduring the reaction of material gas. In addition, the hydrogen or H₂O iscontained in the silicon oxide film. Besides, if a silicon oxide film isformed by performing heat treatment for an SOG film, hydrogen or H₂O isgenerated by this heat treatment.

[0009] On the other hand, in case of an FeRAM having a peripheralcircuit or a logic circuit provided around a memory cell formationregion, multilayer wirings are provided if the logic circuit becomescomplex.

[0010] Since interlayer insulating films are formed between these pluralwirings, respectively, it is becoming more important to take measuresagainst hydrogen or H₂O.

[0011] An object of the present invention is to provide a technique forpreventing film quality of a ferroelectric film constituting acapacitive element from being degraded.

[0012] Another object of the present invention is to provide a techniquefor improving the film quality of the ferroelectric film and thereby forimproving characteristics of a FeRAM memory cell.

[0013] The above and other objects and novel features of the presentinvention will become apparent from description of the presentspecification and accompanying drawings.

[0014] Of inventions disclosed by the present application, the outlineof representative ones will be briefly described as follows.

[0015] (1) A semiconductor integrated circuit device according to thepresent invention is a semiconductor integrated circuit device having aninformation transfer MISFET formed on a main surface of a semiconductorsubstrate, and a capacitor connected in series to said informationtransfer MISFET, wherein it has a first shielding film formed under alower electrode and a second shielding film formed on the upperelectrode of said capacitor.

[0016] According to means as described above, the first and secondshielding films can prevent H₂ or H₂O from entering an upper or lowerportions of the capacitor and prevent the characteristics of ahigh-dielectric-constant material or ferroelectric material (capacitiveinsulating film) from being degraded in the capacitor. In addition, thefirst and second shielding films can reduce diffusion of the components,e.g., lead included in the capacitive insulating film. The first andsecond shielding films may be made of lead compounds. Also, thecapacitive insulating film may be made of a lead compound. If a leadcomposition ratio of each of the first and second shielding films is sethigher than that of the capacitive insulating film, then lead diffusedfrom the capacitive insulating film can be compensated by lead includedin the first and second shielding films. Thereby, it is possible toprevent the characteristics of the capacitive insulating film from beingdegraded. The lead compound is exemplified by PZT(Pb_(x)(Zr_(y)Ti_(z))O₃) or the like. In addition, if said upper orlower electrode is covered with the first and second shielding films,for example, by forming a side wall film on the side wall of the upperor lower electrode, or the like, then the present invention becomes moreeffective.

[0017] (2) A semiconductor integrated circuit device according to thepresent invention is a semiconductor integrated circuit device having aninformation transfer MISFET formed on a main surface of a semiconductorsubstrate, and a capacitor connected in series to the informationtransfer MISFET, wherein it has a shielding film formed under the lowerelectrode of said capacitor.

[0018] According to means as described above, the shielding film canprevent H₂ or H₂O from entering the lower portion of the capacitor andprevent the characteristics of the high-dielectric-constant material orferroelectric material (capacitive insulating film) from being degradedin the capacitor. In addition, the shielding film can reduce diffusionof the components, e.g., lead included in the capacitive insulatingfilm. Further, it is possible to improve the crystallinity of thecapacitive insulating film on the shielding film. Since the insulatingfilm under a region in which the capacitor is formed contains hydrogenby hydrogen annealing treatment, in particular, it is possible toprevent entry of the hydrogen. This shielding film may be made of a leadcompound. Also, the capacitive insulating film may be made of a leadcompound. If the lead composition ratio of the shielding film is sethigher than that of the capacitive insulating film, lead diffused fromthe capacitive insulating film can be compensated by lead included inthe shielding film. Therefore, it is possible to prevent thecharacteristics of the capacitive insulating film from being degraded.The lead compound is exemplified by PZT (Pb_(x)(Zr_(y)Ti₂)O₃) or thelike.

[0019] (3) A semiconductor integrated circuit device according to thepresent invention is a semiconductor integrated circuit device having aninformation transfer MISFET formed on a main surface of a semiconductorsubstrate, and a capacitor connected in series to the informationtransfer MISFET, wherein is has an interlayer insulating film formed onthe information transfer MISFET and the capacitor, the interlayerinsulating film which has a barrier layer made of ahigh-dielectric-constant material or a ferroelectric material.

[0020] According to means as described above, the barrier layer canprevent H₂ or H₂O included in the interlayer insulating film fromentering the capacitor and prevent the high-dielectric-constant materialor ferroelectric material (capacitive insulating film) from beingdegraded in the capacitor. This barrier layer may be made of a leadcompound. The lead compound is exemplified by PZT (Pb_(x)(Zr_(y)Ti₂)O₃)or the like. This barrier layer may be amorphous. The barrier layer maybe formed so as to be put between the first and second insulating films.Also, in the case where a plug is formed in the interlayer insulatingfilm, the bottom and side portions of the plug may be covered with aconductive film having a barrier property such as a TiN film or thelike. Further, the barrier layer may be formed in all the interlayerinsulating films between multi-layer wirings. In addition, the barrierlayer may be formed in a passivation film formed on the uppermostwiring. Besides, the barrier layer may be formed only in the memory cellformation region without being formed in the peripheral circuit region.

[0021] (4) A manufacturing method of a semiconductor integrated circuitdevice according to the present invention comprises the steps of:forming an information transfer MISFET formed on a main surface of asemiconductor substrate; forming an insulating film on said MISFET; andsequentially depositing a shielding film, a first conductive film, acapacitive insulating film made of a ferroelectric material, and asecond conductive film on said insulating film, and patterning thesefilms, and thereby forming, on the shielding film, a capacitorconstituted by a lower electrode made of the first conductive film, acapacitive insulating film, and an upper electrode made of the secondconductive film.

[0022] According to means as described above, it is possible tomanufacture a semiconductor integrated circuit device capable ofpreventing the characteristics of the high-dielectric-constant materialor ferroelectric material (capacitive insulating film) from beingdegraded in the capacitor. In the case where the insulating filmcontains hydrogen by hydrogen annealing treatment, in particular, thishydrogen can be prevented from entering the capacitive insulating film.Also, if said insulating film is formed by a plasma CVD method or byperforming heat treatment for an SOG film, it is possible to prevententry of hydrogen or H₂O generated by the treatment. Further, ashielding film may be formed even on the upper electrode. This shieldingfilm may be made of a lead compound. The lead compound is exemplified byPZT (Pb_(x)(Zr_(y)Ti₂)O₃) or the like.

[0023] (5) A manufacturing method of a semiconductor integrated circuitdevice according to the present invention comprises the steps of:forming an information transfer MISFET and a capacitor which are formedon a main surface of a semiconductor substrate; sequentially depositingan insulating film, a barrier layer made of a high-dielectric-constantmaterial or ferroelectric material, and a second conductive film, on theinformation transfer MISFET and the capacitor, and thereby forming aninterlayer insulating film.

[0024] According to means as described above, it is possible tomanufacture a semiconductor integrated circuit device capable ofpreventing the characteristics of the high-dielectric-constant materialor ferroelectric material (capacitive insulating film) from beingdegraded in the capacitor. In the case where the insulating film isformed by a plasma CVD method or by performing heat treatment for an SOGfilm, in particular, the barrier layer can prevent hydrogen or H₂Ogenerated by the treatment from entering the capacitor. This barrierlayer may be made of a lead compound. The lead compound is exemplifiedby PZT (Pb_(x)(Zr_(y)Ti₂)O₃) or the like.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025]FIG. 1 is a cross-sectional view of a principal portion of asubstrate for showing a manufacturing method of a semiconductorintegrated circuit device that is a first embodiment of the presentinvention.

[0026]FIG. 2 is a cross-sectional view of a principal portion of asubstrate for showing the manufacturing method of a semiconductorintegrated circuit device that is the first embodiment of the presentinvention.

[0027]FIG. 3 is a cross-sectional view of a principal portion of asubstrate for showing the manufacturing method of a semiconductorintegrated circuit device that is the first embodiment of the presentinvention.

[0028]FIG. 4 is a cross-sectional view of a principal portion of asubstrate for showing the manufacturing method of a semiconductorintegrated circuit device that is the first embodiment of the presentinvention.

[0029]FIG. 5 is a cross-sectional view of a principal portion of asubstrate for showing the manufacturing method of a semiconductorintegrated circuit device that is the first embodiment of the presentinvention.

[0030]FIG. 6 is a cross-sectional view of a principal portion of asubstrate for showing the manufacturing method of a semiconductorintegrated circuit device that is the first embodiment of the presentinvention.

[0031]FIG. 7 is a cross-sectional view of a principal portion of asubstrate for showing the manufacturing method of a semiconductorintegrated circuit device that is the first embodiment of the presentinvention.

[0032]FIG. 8 : is a cross-sectional view of a principal portion of asubstrate for showing the manufacturing method of a semiconductorintegrated circuit device that is the first embodiment of the presentinvention.

[0033]FIG. 9 is a cross-sectional view of a principal portion of asubstrate for showing the manufacturing method of a semiconductorintegrated circuit device that is the first embodiment of the presentinvention.

[0034]FIG. 10 is a cross-sectional view of a principal portion of asubstrate for showing the manufacturing method of a semiconductorintegrated circuit device that is the first embodiment of the presentinvention.

[0035]FIG. 11 is a cross-sectional view of a principal portion of asubstrate for showing the manufacturing method of a semiconductorintegrated circuit device that is the first embodiment of the presentinvention.

[0036]FIG. 12 is a cross-sectional view of a principal portion of asubstrate for showing the manufacturing method of a semiconductorintegrated circuit device that is the first embodiment of the presentinvention.

[0037]FIG. 13 is a cross-sectional view of a principal portion of asubstrate for showing the manufacturing method of a semiconductorintegrated circuit device that is the first embodiment of the presentinvention.

[0038]FIG. 14 is a cross-sectional view of a principal portion of asubstrate for showing the manufacturing method of a semiconductorintegrated circuit device that is the first embodiment of the presentinvention.

[0039]FIG. 15 is a cross-sectional view of a principal portion of asubstrate for showing the manufacturing method of a semiconductorintegrated circuit device that is the first embodiment of the presentinvention.

[0040]FIG. 16 is a cross-sectional view of a principal portion of asubstrate for showing the manufacturing method of a semiconductorintegrated circuit device that is the first embodiment of the presentinvention.

[0041]FIG. 17 is a cross-sectional view of a principal portion of asubstrate for showing the manufacturing method of a semiconductorintegrated circuit device that is the first-embodiment of the presentinvention.

[0042]FIG. 18 is a cross-sectional view of a principal portion of asubstrate for showing the manufacturing method of a semiconductorintegrated circuit device that is the first embodiment of the presentinvention.

[0043]FIG. 19A is a cross-sectional view of a principal portion of asubstrate for showing a manufacturing method of a semiconductorintegrated circuit device that is a second embodiment of the presentinvention.

[0044]FIG. 19B is a cross-sectional view of a principal portion of asubstrate for showing the manufacturing method of a semiconductorintegrated circuit device that is the second embodiment of the presentinvention.

[0045]FIG. 19C is a cross-sectional view of a principal portion of asubstrate for showing the manufacturing method of a semiconductorintegrated circuit device that is the second embodiment of the presentinvention.

[0046]FIG. 19D is a cross-sectional view of a principal portion of asubstrate for showing the manufacturing method of a semiconductorintegrated circuit device that is the second embodiment of the presentinvention.

[0047]FIG. 20A is a cross-sectional view of a principal portion of asubstrate for showing a manufacturing method of a semiconductorintegrated circuit device that is a third embodiment of the presentinvention.

[0048]FIG. 20B is a cross-sectional view of a principal portion of asubstrate for showing the manufacturing method of a semiconductorintegrated circuit device that is the third embodiment of the presentinvention.

[0049]FIG. 20C is a cross-sectional view of a principal portion of asubstrate for showing the manufacturing method of a semiconductorintegrated circuit device that is the third embodiment of the presentinvention.

[0050]FIG. 20D is a cross-sectional view of a principal portion of asubstrate for showing the manufacturing method of a semiconductorintegrated circuit device that is the third embodiment of the presentinvention.

[0051]FIG. 21A is a cross-sectional view of a principal portion of asubstrate for showing a manufacturing method of a semiconductorintegrated circuit device that is a fourth embodiment of the presentinvention.

[0052]FIG. 21B is a cross-sectional view of a principal portion of asubstrate for showing the manufacturing method of a semiconductorintegrated circuit device that is the fourth embodiment of the presentinvention.

[0053]FIG. 21C is a cross-sectional view of a principal portion of asubstrate for showing the manufacturing method of a semiconductorintegrated circuit device that is the fourth embodiment of the presentinvention.

[0054]FIG. 22 is a cross-sectional view of a principal portion of asubstrate for showing a manufacturing method of a semiconductorintegrated circuit device that is a fifth embodiment of the presentinvention.

[0055]FIG. 23 is a cross-sectional view of a principal portion of asubstrate for showing the manufacturing method of a semiconductorintegrated circuit device that is the fifth embodiment of the presentinvention.

[0056]FIG. 24 is a plane view of a principal portion of a substrate forshowing a manufacturing method of a semiconductor integrated circuitdevice that is a sixth embodiment of the present invention.

[0057]FIG. 25 is a plane view of a principal portion of a substrate forshowing the manufacturing method of a semiconductor integrated circuitdevice that is the sixth embodiment of the present invention.

[0058]FIG. 26 is a view shows a circuit arrangement of a FeRAM memorycell that is a seventh embodiment of the present invention.

[0059]FIG. 27 is a view shows another circuit arrangement of a FeRAMmemory cell that is a seventh embodiment of the present invention.

[0060]FIG. 28 is a cross-sectional view of a principal portion of asubstrate showing a FeRAM memory cell that is an eighth embodiment ofthe present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0061] Embodiments of the present invention will be describedhereinafter in detail with reference to the drawings. It is noted thatconstituent elements having the same functions are denoted by the samereference numbers in all the drawings for describing the embodiments ofthe present invention and repetitive description thereof will beomitted.

[0062] (First Embodiment)

[0063] A manufacturing method of a FeRAM, which is a first embodiment ofthe present invention, will be described hereinafter with reference toFIGS. 1 to 18 in order of manufacturing steps.

[0064] First, as shown in FIG. 1, a p-type well 3 and an n-type well 4are formed in a semiconductor substrate 1 composed of an n-typemono-crystalline silicon having a resistivity of about 10 Ωcm. Thep-type well 3 is formed by ion-implanting p-type impurities such asboron (B) into the semiconductor substrate 1, and then by annealing thesemiconductor substrate 1 to thermally diffuse the impurities. Then-type well 4 is formed by ion-implanting n-type impurities such asphosphor (P) into the semiconductor substrate 1, and then by annealingthe semiconductor substrate to thermally diffuse the impurities.

[0065] Next, a field oxide film 2 for element isolation is formed on themain surface of the semiconductor substrate 1. This field oxide film 2is formed by a well-known LOCOS (Local Oxidation of Silicon) method.

[0066] Then, a hydrofluoric acid cleaning solvent is used towet-cleaning the surface of the semiconductor substrate 1 (the p-typewell 3 and the n-type well 4), and thereafter wet-oxidation isperformed, and a clean gate oxide film 5 are formed on each surface ofthe p-type well 3 and the n-type well 4.

[0067] Next, a conductive layer such as a poly-crystalline silicon filmis deposited on an upper portion of the gate oxide film 5, and then asilicon oxide film or the like is deposited thin and is patterned. Bythis, a capacitive element D having the poly-crystalline silicon film asa lower electrode FG and the silicon oxide film as a capacitiveinsulating film 6, is formed on the wide field oxide film 2 in then-type well 4. An upper electrode of this capacitive element D is formedsimultaneously with the gate electrodes SG of MISFETs Qs and Qp formedon the main surfaces of the p-type well 3 and the n-type well 4,respectively.

[0068] Next, a conductive film such as a poly-crystalline silicon filmor the like is deposited on the upper portion of the semiconductorsubstrate 1 and is patterned. By this, the gate electrodes SG are formedon the main surfaces of the p-type well 3 and the n-type well 4,respectively. Further, conductive layers SG1 used for wiring, resistanceand the like are formed on the field oxide film 2. Also, an upperelectrode SG2 is formed on the capacitive insulating film 6.

[0069] Next, n-type impurities such as phosphor (P) are ion-implantedinto both sides of the gate electrode SG on the p-type well 3 to therebyform n-type semiconductor regions 7 (source and drain). Also, p-typeimpurities such as boron (B) are ion-implanted into both sides of thegate electrode SG on the n-type well 4 to thereby form p-typesemiconductor regions 8 (source and drain). Then, a BPSG film 9 isdeposited on the upper portion of the semiconductor substrate 1. It isnoted that this BPSG film 9 may be used as a TEOS film or a SOG film asdescribed later.

[0070] Thereafter, annealing is performed in hydrogen atmosphere so asto remedy defects on interfaces between each n-type semiconductorregions 7 and one of the gate oxide films 5, and between each p-typesemiconductor region 8 and the other of the gate oxide films 5.

[0071] Through the above-described steps, the n-channel type MISFET Qsconstituting an FeRAM and a p-channel type MISFET Qp constituting aperipheral circuit are formed.

[0072] Next, as shown in FIG. 2, a PPZT film B1 used as a shielding filmis deposited on the silicon oxide film 9 by a sputtering method. Then, alaminating film 10 composed of a Ti film and a Pt film and used as alower electrode is deposited. A PZT film 11 is then deposited.

[0073] Composition of the PZT film will now be described. PZT isrepresented by Pb (Zr_(y)Ti_(z)) O₃ (y+z=1). Composition ratio of theseatoms constituting the PZT film is introduced from a crystal structureof PZT. Pb atoms in PZT are arranged one by one in each of eight cornersof a cube, and a Zr or Ti atom is located at substantially a center ofthe cube. Further, oxygen atoms are arranged at substantially a centerof each plane of the cube. This follows that one (⅛×8) Pb atom, one Zror Ti atom, and three (½×6) oxygen atoms exist in the cube. It is noted,however, that lead oxide exists in such a grain boundary.

[0074] Further, Pb atoms in PZT have a characteristic of easilyvolatilizing. Due to this, when the PZT film 11 is formed, an amorphousfilm having a Pb composition ratio of 1+α₁ is deposited. This amorphousfilm is crystallized by annealing performed after formation of the PZTfilm 11.

[0075] As will be described later in detail, the PZT film B1 formed asthe shielding film has a Pb composition ratio of 1+α₂ (α₂>α₁) at thetime of formation thereof in order to compensate for Pb released fromthe PZT film 11. While being formed, this PZT film B1 is amorphous, too.

[0076] Thereafter, annealing is performed to crystallize the PZT film11. At this time, the PZT film B1 is crystallized, too. Then, a Pt film12 used as an upper electrode is deposited on the PZT film 11.Subsequently, by patterning the Pt film 12, an upper electrode 12 a isformed on an upper portion of the wide field oxide film 2 in the p-typewell 3.

[0077] Next, as shown in FIG. 3 , a PZT film B2 used as a shielding filmis deposited on the upper electrode 12 a and the PZT film 11 by thesputtering method. This PZT film. B2 also has a Pb composition ratio of1+α₂ (α₂>α₁) at the time of formation thereof in order to compensate forPb released from the PZT film 11. The PZT film B2 too is amorphous whenbeing formed.

[0078] Next, as shown in FIG. 4, a resist film (not shown) is formed onan upper portion of the upper electrode 12 a. Then, by using this resistmask as a mask and by plasma-etching the PZT film B2, a shielding filmB2 a is formed on the upper electrode 12 a. At this time, if patterns ofthe shielding film B2 a are formed larger than those of the upperelectrode 12 a, side portions of the upper electrode 12 a are alsocovered with the shielding film B2 a to thereby be capable of increasingfurther a shielding effect. Next, the resist film is removed by ashing.Then, annealing is performed to remedy defects of the PZT film 11generated by plasma-etching and annealing.

[0079] Next, a resist film (not shown) is formed on upper portions ofthe upper electrode 12 a and the periphery thereof. By using this resistfilm as a mask and by plasma-etching the PZT film 11, the laminatingfilm 10 composed of both the Ti film and the PT film, and the PZT filmB1, a capacitive insulating film 11 a, a lower electrode 10 a and ashielding film B1 a are formed below the upper electrode 12 a (see FIG.5). Here, the reason why respective patterns of the capacitiveinsulating film 11 a, the lower electrode 10 a and the shielding film B1a are formed larger than patterns of the upper electrode 12 a, is toensure a connection region between the lower electrode 10 a and anintermediate wiring L1 to be described later, on the lower electrode 10a. Then, the resist film is removed by ashing. Annealing is performed toremedy defects of the PZT film 11 generated by plasma-etching andannealing.

[0080] Through the above-described steps, a capacitor C constituting theFeRAM is formed. This capacitor C consists of the upper electrode 12 a,the capacitive insulating film 11 a and the lower electrode 10 a. Theshielding film B2 a covers the upper portion of the upper electrode 12a. The shielding film B1 a is also formed on a lower portion of thelower electrode 10 a.

[0081] As can be seen, in the first embodiment, it is possible toprevent hydrogen or H₂O from entering the capacitive insulating film lha since the shielding films B1 a and B2 a are formed. That is, theshielding films B1 a and B2 a serve as barriers for preventing hydrogenor H₂O from passing therethrough.

[0082] Further, if entering the PZT film, the hydrogen or the likecombines with oxygen atoms and thereby film quality of the PZT film isdegraded. In this embodiment, however, even if hydrogen or the likeenters the shielding films B1 a and B2 a, then oxygen included in theshielding films B1 a and B2 a becomes reaction object as reactingtherewith and thereby it is possible to be prevented from reacting withoxygen atoms included in the capacitive insulating film 11 a. In otherwords, the shielding films B1 a and B2 a themselves become sacrificesand influence of hydrogen or the like can be therefore reduced relativeto the capacitive insulating film 11 a.

[0083] Furthermore, Pt used in the upper electrode 12 a and the lowerelectrode 10 a has a catalytic action to transform H₂ to H⁺ (hydrogenions). In the case where the hydrogen ions are diffused into the upperelectrode 12 a or the lower electrode 10 a and enter the capacitiveinsulating film 11 a, it is considered that a crystalline characteristicthereof is destroyed. In this embodiment, however, since the shieldingfilm B2 a is formed on the upper electrode 12 a and the shielding filmB1 a is formed below the lower electrode 10 a, lead oxide included inthe shielding films are diffused into these electrodes 10 a and 12 a.This lead oxide serves as a catalyst poison and can restrain catalyticaction of Pt described above. This lead oxide can be diffused into theelectrodes 10 a and 12 a by performing heat treatment at a temperatureof 550° C. or higher.

[0084] As a method for making such lead oxide serving as a catalystpoison contain in the lower electrode 10 a and the upper electrode 12 a,the Pt film may be made to contain Pt oxide therein in advance during astep of forming the Pt film for providing the lower electrode 10 a andthe upper electrode 12 a.

[0085] Meanwhile, as having already described above, since Pb has acharacteristic of easily volatilizing, Pb included in the capacitiveinsulating film 11 a is diffused and thereby defects are caused. In thisembodiment, however, since the Pb composition ratio of the PZTconstituting each of the shielding films B1 a and B2 a is set large(α₂>α₁), it is possible to compensate for defects of Pb included in thecapacitive insulating film 11 a. Namely, Pb included in the shieldingfilms B1 a and B2 a are supplied into the capacitive insulating film 11athrough either the upper electrode 12 a or the lower electrode 10 a,and thereby the defects are remedied.

[0086] Furthermore, in particularly, by forming the shielding film B1 abelow the lower electrode 10 a, influence of H₂ included in the BPSGfilm 9 generated by the above-stated hydrogen annealing can be reduced.In addition, by forming the shielding film B1 a using the same materialbelow the lower electrode 10 a, it is possible to improve a crystallinecharacteristic of the lower electrode 10 a. Additionally, in the casewhere the shielding film B1 a is crystallized by annealing and then thecapacitive insulating film is formed, it is possible to improve furtherthe crystalline characteristic of the lower electrode 10 a.

[0087] Consequently, in the first embodiment, it is possible to ensurethe characteristic of the capacitive insulating film 11 a and toincrease a residual polarization amount Qsw. It is also possible torestrain dispersion of the residual polarization amount Qsw.

[0088] Next, a silicon oxide film (to be referred to as “TEOS film”hereinafter) 13 made of a material of tetraethoxysilane is deposited bya CVD method, as shown in FIG. 6.

[0089] Subsequently, a resist film (not shown) having opening portionslocated on the n-type semiconductor region 7 (source and drain), thep-type semiconductor region 8 (source and drain) and the lower electrodeFG of the capacitive element D, is formed on the TEOS film 13. Then, asshown in FIG. 7, by using this resist film as a mask and byplasma-etching and removing the silicon oxide films 9 and 13 located ofthe n-type semiconductor region 7 (source and drain) and the p-typesemiconductor region 8 (source and drain), contact holes C1 are formed.The resist film is removed by ashing, and thereby a Pt film (not shown)is formed on the TEOS film 13 and in each interior of the contact holesC1. Next, silicide layers 14 are formed on contact portions between thePt film, and each of the n-type semiconductor region 7 (source anddrain) and the p-type semiconductor region (source and drain) and thelower electrode FG of the capacitive element D. The Pt film not reactedis then removed.

[0090] Next, a resist film (not shown) having opening portions locatedon the upper electrode 12 a and the lower electrode 10 a of thecapacitor C is formed. Subsequently, as shown in FIG. 8, the shieldingfilm B2 a and the TEOS film 13 located on the upper electrode 12 a, andthe TEOS film 13 and the capacitive insulating film 11 a located on thelower electrode 10 a are removed by a plasma etch, and thereby contactholes C2 are formed. The resist film is removed by ashing, and isannealed in O₂ (oxygen) atmosphere in order to improve film quality ofthe PZT film.

[0091] Subsequently, a resist film (not shown) having opening portionslocated on the conductive layer SG1 provided on the field oxide film 2and on the upper electrode SG2 of the capacitive element D, is formed.Then, as shown in FIG. 9, the silicon oxide films 9 and 13 located onthe conductive film SG1 and the upper electrode SG2 are removed byplasma etching, and thereby contact holes C3 is formed. The resist filmis then removed by ashing.

[0092] Next, as shown in FIG. 10, a TiN film 16 is deposited on the TEOSfilm 13 and in each interior of the contact holes C1, C2 and C3. The TiNfilm 16 is patterned to thereby form intermediate wirings L1. By theintermediate wirings L2, the n-channel type MISFETQs and the capacitor Care connected in series. Namely, the n-type semiconductor region 7(source and drain) of the n-channel type MISFETQs and the upperelectrode 12 a of the capacitor C are connected by one of theintermediate wirings L1.

[0093] Next, as shown in FIG. 11, a TEOS film 17 is formed on theintermediate wirings L1 and the TEOS film 13.

[0094] Thereafter, a first to third layer wirings M1 to M3 are formed onthe TEOS film 17. Now, description will be in detail given to the stepsof forming these wirings and the steps of forming interlayer insulatingfilms S1 to S3 to be provided between the wirings, respectively.

[0095] First, a resist film (not shown) having opening portions isformed on the TEOS film 17. The opening portions are formed, forexample, on the lower electrode 10 a of the capacitor C, on the n-typesemiconductor region 7 (source and drain) not connected to the capacitorC of the n-channel type MISFET Qs or the p-type semiconductor region 8(source and drain) located in a peripheral circuit region, on theelectrodes FG and SG2 of the capacitive element D and the like. Next, asshown in FIG. 12, the TEOS film 17 is etched by using this resist filmas a mask, and thereby contact holes 18 are formed.

[0096] Next, a TiN film, an Al film, and a TiN film are sequentiallydeposited on the TEOS film 17 and in each interior of the contact holes18. These interlayer films are patterned to thereby form the first layerwirings M1 (see FIG. 13).

[0097] Subsequently, as shown in FIG. 14, a TEOS film S1 a, a PZT filmS1 b used as a barrier film, and a TEOS film S1 c are sequentiallydeposited on the first layer wirings M1 and the TEOS film 17, andthereby an interlayer insulating film S1 is formed, which consists ofthe above-stated films. The PZT film S1 b is an amorphous film having aPb composition ratio of 1+α₃. After the PZT film S1 b is formed, no heattreatment is performed at high temperature. Due to this, the PZT film S1b is not crystallized but remain amorphous.

[0098] As can be seen, in this embodiment, since the PZT film S1 bserving as a barrier film is formed in the interlayer insulating filmS1, it is possible to prevent hydrogen or H₂O from entering thecapacitive insulating film 11 a. That is, the PZT film S1 b serves as abarrier and prevents hydrogen or H₂O existing in the TEOS film S1 c anda TEOS film S2 a to be described later, from passing therethrough.Particularly, since the PZT film S1 b is amorphous and does not have agrain boundary, it can prevent hydrogen or H₂O from passing therethroughmore effectively than the crystallized PZT film.

[0099] Further, since hydrogen, H₂O or the like existing in the TEOSfilms S1 a and S1 c combines with oxygen atoms included in the PZT filmS1 b, it is possible to prevent hydrogen or H₂O from entering thecapacitive insulating film 11 a. It is also possible to prevent areaction to oxygen atoms included in the capacitive insulating film 11a. That is, the PZT film S1 b itself becomes a sacrifice, so that it ispossible to reduce the influence of hydrogen or the like relative to thecapacitive insulating film 11 a.

[0100] Next, a resist film (not shown) having opening portions indesired regions located on the first layer wirings M1, is formed on theinterlayer insulating film S1. By using this resist film as a mask andby etching the interlayer insulating film S1, contact holes 19 areformed (see FIG. 15).

[0101] Next, a TiN film, an Al film and a TiN film are sequentiallydeposited on the interlayer insulating film S1 and in each interior ofthe contact holes 19. These laminating films are patterned to therebyform the second layer wirings M2 (FIG. 16).

[0102] Here, although the PZT film S1 b serving as a barrier film isremoved by forming the contact holes 19, the TiN film (or barrier metalfilm) is formed in the contact holes 19 as described above. This TiNfilm has a barrier property of preventing hydrogen or the like frompassing therethrough. It is, therefore, possible to prevent hydrogen orthe like from entering the inside thereof through each of the contactholes 19. That is, the PZT film S1 b or the TiN film covers thesemiconductor substrate 1, so that hydrogen or H₂O can be prevented fromentering the capacitive insulating film 11 a by this film.

[0103] Next, as shown in FIG. 17, a TEOS film S2 a, a PZT film S2 bserving as a barrier film, and a TEOS film S2 c are sequentiallydeposited on the second layer wirings M2 and the interlayer insulatingfilm S1, and thereby an interlayer insulating film S2 is formed, whichconsists of the above-stated films. This PZT film S2 b is an amorphousfilm having a Pb composition ratio of 1+α₃ similarly to the PZT film S1b.

[0104] As can be seen, in this embodiment, since the PZT film S2 bserving as a barrier film is formed in the interlayer insulating filmS2, it is possible to prevent hydrogen or H₂O from entering thecapacitive insulating film 11 a. That is, the PZT film Sb2 serves as abarrier and prevents hydrogen or H₂O existing in the TEOS film S2 c anda TEOS film S3 a to be described later, from passing therethrough.Particularly, since the PZT film S2 b is amorphous and has no grainboundary, it can prevent hydrogen or H₂O from passing therethrough moreeffectively than the crystallized PZT film.

[0105] Further, since hydrogen, H₂O or the like existing in the TEOSfilms S2 a and S2 c combines with oxygen atoms included in the PZT filmS2 b, it is possible to prevent hydrogen or H₂O from entering thecapacitive insulating film 11 a. It is also possible to prevent hydrogenor H₂O from reacting with oxygen atoms included in the capacitiveinsulating film 11 a. That is, the PZT film S2 b itself becomes asacrifice, and it is possible to reduce influence of hydrogen or thelike relative to the capacitive insulating film 11 a.

[0106] Moreover the PZT film S1 b or S2 b is not crystallized but remainamorphous. Due to this, in comparison with the crystallized PZT film, itis possible to keep permittivity of thereof low. By keeping thepermittivity of the PZT film S1 b or S2 b low, it is possible to reducerespective parasitic capacities between the first layer wirings M1 andthe second layer wirings M2 and between the second layer wirings M2 andthe third layer wiring M3, and therefore to achieve a high speed ofcircuit operation in the memory cell.

[0107] Next, a resist film (not shown) having opening portions indesired regions located on the second layer wirings M2 is formed on theinterlayer insulating film S2. By using this resist film as a mask andby etching the interlayer insulating film S2, a contact hole 20 isformed.

[0108] Then, a TiN film, an Al film and a TiN film are sequentiallydeposited on the interlayer insulating film S2 and in an interior of thecontact hole 20. Next, by patterning these films, the third layer wiringM3 is formed (see FIG. 18).

[0109] Here, although the PZT film S2 b serving as a barrier film isremoved by forming the contact hole 20, the TiN film (or a barrier metalfilm) is formed in the contact hole 20 as stated above. This TiN filmhas such a barrier characteristic that hydrogen or the like can not passtherethrough, and thereby it is possible to prevent hydrogen or the likefrom entering the inside thereof through the contact holes 20. That is,the PZT film S2 b or the TiN film covers the semiconductor substrate 1,and thereby it is possible to prevent hydrogen or H₂O from entering thecapacitive insulating film 11 a by this film.

[0110] Next, as shown in FIG. 18, a TEOS film S3 a, a PZT film S3 b usedas a barrier film, and an a TEOS film S3 c are sequentially deposited onthe third layer wiring M3 and the interlayer insulating film S2, andthereby an interlayer insulating film S3 is formed, which consists ofthe above-stated films. This PZT film S3 b is also an amorphous filmhaving a Pb composition ratio of 1+α₃ when being formed, similarly tothe PZT film S1 b. Next, a PIQ film 21 is formed on the interlayerinsulating film S3. The interlayer insulating film S3 and the PIQ film2lare formed on the uppermost layer wiring M3 and are used as films(passivation films) for protecting elements and wirings provided on thesemiconductor substrate.

[0111] As can be seen, in this embodiment, since the PZT film S3 bserving as a barrier film is formed in the interlayer insulating filmS3, it is possible to prevent hydrogen or H₂O from entering thecapacitive insulating film 11 a. That is, the PZT film S3 b serves as abarrier and prevents hydrogen or H₂O existing in the TEOS film S3 andthe PIQ film from entering the inside thereof.

[0112] Further, since hydrogen, H₂O or the like existing in the TEOSfilms S3 a and S3 c combines with oxygen atoms included in the PZT filmS3 b, it is possible to prevent hydrogen or H₂O from entering thecapacitive insulating film 11 a. It is also possible to prevent hydrogenor H₂O from reacting with oxygen atoms included in the capacitiveinsulating film 11 a. That is, the PZT film S3 b itself becomes asacrifice, and thereby it is possible to reduce influence of hydrogen orthe like relative to the capacitive insulating film 11 a.

[0113] In the present embodiment, TEOS films or the like are used toform the interlayer insulating films S1 and the like, but may also beformed by using SOG films or the like. Since an SOG film contains muchmoisture, forming the barrier layers S1 b and S2 b and the like in theinterlayer insulating films S1 causes much effect.

[0114] And, in this embodiment, although the PZT films are used as thebarrier layers S1 b and S2 b in the interlayer insulating films S1, aAl₂O₃ film or the like may be used as a barrier layer. In this Al₂O₃film, diffusive speed of hydrogen or H₂O is slow, so that it is possibleto reduce influence of hydrogen or the like relative to the capacitiveinsulating film 11 a.

[0115] (Second Embodiment)

[0116] In the first embodiment, after forming the shielding film B2 a,the PZT film 11, the laminating film 10 consisting of the Ti film andthe Pt film, and the PZT film B1 are etched. However, by forming a PZTfilm B3 after this etch, a side wall PZT film B3 a may be formed in sidewalls of the lower electrode 10 a.

[0117] First, a semiconductor substrate shown in FIG. 4 is prepared. Thesteps of forming the semiconductor substrate shown in FIG. 4 are thesame as the case of the first embodiment, and thereby descriptionthereof will be omitted. FIG. 19A is an enlarged view of a vicinity ofthe shielding film B2 a (capacitor C part) in the semiconductorsubstrate shown in FIG. 4. As shown in FIG. 19A, a PZT film B1, alaminating film 10 consisting of a Ti film and a Pt film, and a PZT film11 are formed on-the BPSG film 9. Also, the upper electrode 12 a isformed on this PZT film 11, and an upper portion and a side portion ofthe upper electrode 12 a are covered with the shielding film B2 a.

[0118] Next, as shown in FIG. 19B, by plasma-etching the PZT film 11,and the laminating film 10 consisting of the Ti film and the Pt film, acapacitive insulating film 11 a and a lower electrode 10 a are formedbelow the upper electrode 12 a. At this time, the side portion of thelower electrode 1a are not covered with the shielding film B2 a.

[0119] Then, as shown in FIG. 19C, a PZT film B3 is deposited on aregion including a formation region of the lower electrode 10 a by asputtering method.

[0120] Here, the PZT film B3 is also an amorphous film having a Pbcomposition ratio of 1+α₂ (α₂>α₁) when being formed, similarly to thePZT films B1 and B2.

[0121] Next, by using a pattern slightly smaller than the lowerelectrode 10 a, the PZT film B3 located above the lower electrode 10 ais removed. Following this, by using a pattern slightly larger than thelower electrode 10 a, the PZT films B3 and B1 located around the lowerelectrode 10 a are removed.

[0122] Through the above-described steps, it is possible to form a sidewall PZT film B3 a covering the side walls of the lower electrode 10 a.

[0123] Next, as shown in FIG. 19D, a TEOS film 13 is deposited by a CVDmethod. Since steps following this are the same as the steps of thefirst embodiment described with reference to FIGS. 7 to 18, descriptionthereof will be omitted.

[0124] As can be seen, in the second embodiment, since the side walls ofthe lower electrode 10 a is covered with the side wall PZT film B3 a, itis also possible to prevent H₂ or H₂O from entering the capacitiveinsulating film from the side portions of the lower electrode 10 a, inaddition to effects generated by the shielding films B1 a and B2 adescribed in the first embodiment.

[0125] (Third Embodiment)

[0126] In the second embodiment, although the side wall PZT film B3 a isformed by patterning, the side wall PZT film may be also formed byanisotropic etch.

[0127] First, a semiconductor substrate shown in FIG. 4 is prepared.Since steps of forming the semiconductor substrate shown in FIG. 4 arethe same as the case of the first embodiment, description thereof willbe omitted. FIG. 20A is an enlarged view of a vicinity of the shieldingfilm B2 a (capacitor C part) of the semiconductor substrate shown inFIG. 4. As shown in FIG. 20A, a PZT film B1, a laminating film 10consisting of a Ti film and a Pt film, and the PZT film 11 are formed ona BPSG film 9. Also, an upper electrode 12 a is formed on the PZT film11, and an upper and side portions of the upper electrode 12 a arecovered with a shielding film B2 a.

[0128] Next, as shown in FIG. 20B, by plasma-etching the PZT film 11 andthe laminating film 10 of the Ti film and the Pt film, a capacitiveinsulating film 11 a and a lower electrode 10 a are formed below theupper electrode 12 a. At this time, the side portions of the lowerelectrode 10 a are not covered with the shielding film B2 a.

[0129] Subsequently, a PZT film B23 is deposited in a region including aformation region of the lower electrode 10 a by a sputtering method.

[0130] Here, the PZT film 23 is also an amorphous film having a Pbcomposition ratio of 1+α₂ (α₂>α₁) when being formed, similarly to thePZT films B1 and B2.

[0131] Next, as shown in FIG. 20C, by an isotropically etching the PZTfilm B23, a side wall PZT film B23 a is formed on the side walls of thelower electrode 10 a. At this time, the side wall PZT film B23 a is alsoformed on the side walls of the shielding film B2 a.

[0132] Following this, by etching the PZT film B1, a shielding film B1 ais formed below the side wall PZT film B23 a and the lower electrode 10a.

[0133] Next, as shown in FIG. 20D, a TEOS film 13 is deposited by a CVDmethod. Since steps following this are the same as the case of the firstembodiment described with reference to FIGS. 7 to 18, descriptionthereof will be omitted.

[0134] As can be seen, in the third embodiment, since the side walls ofthe lower electrode 10 a is covered with the side wall PZT film B23 a,it is possible to prevent H₂ or H₂O from entering the capacitiveinsulating film 11 a from the side portions of the lower electrode 10 a,similarly to the case of the second embodiment.

[0135] (Fourth Embodiment)

[0136] In the second embodiment, although a PZT film B3 on the lowerelectrode 10 a is removed, it is also possible to omit such the step ofremoving the PZT film B3.

[0137] First, a semiconductor substrate shown in FIG. 4 is prepared.Since steps of forming the semiconductor substrate shown in FIG. 4 arethe same as the case of the first embodiment, description thereof willbe omitted. FIG. 21A is an enlarged view of a vicinity of the shieldingfilm B2 a (capacitor C part) of the semiconductor substrate shown inFIG. 4. As shown in FIG. 21A, a PZT film B1, a laminating film 10consisting of a Ti film and a Pt film, and a PZT film 11 are formedabove a BPSG film 9. Also, an upper electrode 12 a is formed on this PZTfilm 11 a, and an upper portion and a side portion of the upperelectrode 12 a are covered with a shielding film B2 a.

[0138] Next, as shown in FIG. 21B, by plasma-etching the PZT film 11 andthe laminating film 10 consisting of the Ti film, and the Pt film, acapacitive insulating film 11 a and a lower electrode 10 a are formedbelow the upper electrode 12 a. At this time, the side portions of thelower electrode 10 a are not covered with the shielding film B2 a.

[0139] Following this, a PZT film B33 is deposited in a region includinga formation region of the lower electrode 10 a by a sputtering method.

[0140] Here, the PZT film B33 is also an amorphous film having a Pbcomposition ratio of 1+α₂ (α₂>α₁) when being formed, similarly to thePZT films B1 and B2.

[0141] Next, as shown in FIG. 21C, by using a pattern slightly largerthan the lower electrode 10 a, the PZT films B33 and B1 located aroundthe lower electrode 10 a are removed.

[0142] Through the above-described steps, it is possible to form ashield PZT film B33 a covering the side walls of the shielding film B2 aand the lower electrode 10 a.

[0143] Next, a TEOS film 13 is deposited by a CVD method. Since stepsfollowing this are the same as the case of the first embodimentdescribed with reference to FIGS. 7 to 18, description thereof will beomitted.

[0144] As can be seen, in the fourth embodiment, since the side walls ofthe lower electrode 10 a are covered with the shield PZT film B33 a, itis also possible to prevent H₂ or H₂O from entering the capacitiveinsulating film 11 a from the side portions of the lower electrode 10 a,similarly to the case of the second embodiment.

[0145] In this embodiment, the shielding film B33 a remains on the upperelectrode 12 a, so that it is possible to form the upper electrode 12 aand the shielding film B2 a located thereon by using the same mask.

[0146] (Fifth Embodiment)

[0147] The side walls of the lower electrode 10 a may be covered with acapacitive insulating film 11 a as follows.

[0148] First, a semiconductor substrate shown in FIG. 1 is prepared.Since steps of forming the semiconductor substrate shown in FIG. 4 arethe same as the case of the first embodiment, description thereof willbe omitted. FIG. 22A is an enlarged view of a formation region of acapacitor C part to be formed on the semiconductor substrate shown inFIG. 1. As shown in FIG. 22A, a PZT film B1 and a laminating film 10consisting of a Ti film and a Pt film are formed on a BPSG film 9,similarly to the first embodiment.

[0149] Next, as shown in FIG. 22B, by patterning the laminating film 10consisting of the Ti film and the Pt film, a lower electrode 10 a isformed.

[0150] Following this, as shown in FIG. 22C, a PZT film 11 to be used asa capacitive insulating film 11 a is deposited on the PZT film B1 and ina portion located on the lower electrode 10 a. At this time, the sidewalls of the lower electrode 10 a are covered with the PZT film 11 to beused as the capacitive insulating film 11 a. Then, by depositing a Ptfilm on the PZT film 11 and by pattering it, an upper electrode 12 a isformed.

[0151] Next, as shown in FIG. 23A, a PZT film B2 to be used as ashielding film B2 a is deposited on the PZT film 11 and in portionslocated on the upper electrode 12 a. At this time, the side walls of theupper electrode 12 a are covered with the PZT film B2.

[0152] As shown in FIG. 23B, by patterning the PZT films B2 and B11, ashielding film B2 a covering the upper and side portions of the upperelectrode 12 a, a capacitive insulating film 11 a covering the sideportions of the lower electrode 10 a, and a shielding film B1 a coveringa bottom surface of the lower electrode 10 a are formed, respectively.

[0153] Here, each of the PZT films B2, 11 and B1 is a amorphous filmhaving a Pb composition ratio of 1+α₂ (α₂>α₁) when being formed.

[0154] Next, a TEOS film 13 is deposited by a CVD method. Since stepsfollowing this are the same as the case of the first embodimentdescribed with reference to FIGS. 7 to 18, description thereof will beomitted.

[0155] As can be seen, in the fifth embodiment, since the side portionsof the lower electrode 10 a are covered with the capacitive insulatingfilm 11 a, the upper electrode 12 a and the lower electrode 10 a can becovered with these three PZT films (B21, 11 a and B1 a).

[0156] (Sixth Embodiment)

[0157] In the first embodiment, although the PZT film S1 b is formedeven on the n-type well 4 which is the peripheral circuit region (see,for example, FIG. 4), the PZT film S1 b located on the n-type well 4serving as the peripheral circuit region may be removed by etch. Thesame thing is true for the PZT film S2 b. A manufacturing method of asemiconductor integrated circuit device according to the presentembodiment further comprises a step of removing the PZT film S1 blocated on the n-type well 4 which is the peripheral circuit region, byetch after formation of the PZT film S1 b, and the other steps are thesame as the cases of the above-mentioned embodiments. And so,description thereof will be omitted.

[0158]FIG. 24 is a plan view illustrating a semiconductor integratedcircuit substrate after an interlayer insulating film S1 (S2) is formed.As shown in FIG. 24, the interlayer insulating film S1 (S2) having a PZTfilm S1 b (S2 b) is formed on a memory cell formation region in which anFeRAM memory cell is formed, and an interlayer insulating film S51 (S52)which does not include the PZT film S1 b (S2 b) is formed on aperipheral circuit part and a logic part.

[0159] As can be seen, in the present embodiment, since the PZT film S1b (S2 b) located on the peripheral circuit part and the logic part isremoved, it is possible to reduce a parasitic capacity generated by thePZT film. It is also possible to achieve a high speed of circuitoperation in the peripheral circuit part and the logic part.

[0160]FIG. 25 is a plan view showing a semiconductor integrate circuitsubstrate generated after an interlayer insulating film S3 is formed. Asshown in FIG. 25, the interlayer insulating film S3 having a PZT film S3b is formed not only on the peripheral circuit part and the logic partbut also on the memory cell formation region. It is noted, however, thatthe interlayer insulating film S3 (PZT film S3 b) provided on the thirdlayer wiring M3 is removed and pad parts PAD are formed.

[0161] As can be seen, in the present embodiment, the interlayerinsulating film S3 having the PZT film S3 b is formed not only on theperipheral circuit part and the logic part but also on the memory cellformation region in the uppermost layer wiring (corresponding to thethird layer wiring M3 in this case). It is, therefore, possible tosufficiently protect the semiconductor integrated circuit device. It isnoted that since no wiring is formed on the interlayer insulating filmS3, a parasitic capacity generated by the PZT film included in theinterlayer insulating film S3 is out of question.

[0162] (Seventh Embodiment)

[0163] The circuit arrangement of the FeRAM memory cell described in thefirst embodiment will now be described. As described in the firstembodiment, the FeRAM memory cell has the capacitor C and the MISFET Qsconnected in series thereto, and, as shown in FIG. 26, one cell (1T1Ccell) can be constituted by a single capacitor C and an MISFET Qsconnected in series thereto. In this case, the gate electrode of theMISFET Qs is connected to a word line WL, and the source and drainregions of the MISFET Qs, which are not connected to the capacitor C,are connected to a bit line BL. Also, an electrode of the capacitor C,which is not connected to the MISFET Qs, is connected to a drive lineDL.

[0164] In addition, as shown in FIG. 27, one FeRAM memory cell (2T2Ccell) may be constituted by two capacitors C and two MISFETs Qs. In thiscase, too, each gate electrode of the two MISFETs Qs is connected to aword line WL, and each electrode of the two capacitors C, which is notconnected to the MISFETs Qs, is connected to a drive line DL. Also,among two sets of source and drain regions of the two MISFETs Qs, whichare not connected to the capacitors C, one set of source and drainregions is connected to a bit line BL and the other set is connected toa bar bit line/BL.

[0165] (Eighth Embodiment)

[0166] In the FeRAM memory cell described in the first embodiment, thecapacitor C is formed on the wide field oxide film 2 above the p-typewell 3 (see FIG. 6). But, a capacitor C may be formed on the n-typesemiconductor region 7 (source and drain) of the MISFET Qs constitutingthe FeRAM memory cell.

[0167]FIG. 28 illustrates an example of a semiconductor integratedcircuit having a capacitor C formed on an n-type semiconductor region 7(source and drain). As shown in FIG. 28, a plug P1 is formed on then-type semiconductor region 7 of the MISFET Qs. This plug P1 is formedby embedding a conductive film in a contact hole Cl which is formed byremoving both a BPSG film 9 on the source and drain regions of theMISFET Qs and a PZT film B1 thereon.

[0168] A capacitor C is formed above the plug P1. This capacitor C isformed by sequentially depositing a laminating film 10 consisting of aTi film and a Pt film, a PZT film 11, and a Pt film 12 on the PZT filmB1 and in a portion located on the plug P1 and by patterning thesefilms.

[0169] In addition, a PZT film B2 and a TEOS film 17 are formed on thePZT film B1 and in a portion located on an upper electrode 12 a, and acontact hole C2 is formed on the upper electrode 12 a by removing thePZT film B2 and the TEOS film 17.

[0170] A wiring layer Ma is formed on the TEOS film 17 and in aninterior of the contact hole C2.

[0171] On the other hand, a contact hole C3 is formed on the n-typesemiconductor region 7 (source and drain) of the MISFET Qs, which is notconnected to the capacitor C, and a wiring layer Mb is formed on theTEOS film 17 and in an interior of the contact hole C3.

[0172] Accordingly, the upper electrode 12 a and the lower electrode 10a are covered with the PZT films B1 and B2 a, and can thereby obtain thesame advantage as that of the first embodiment.

[0173] Furthermore, in this embodiment, if the capacitor C is formedabove the n-type semiconductor region 7 (source and drain) of the MISFETQs, it is possible to achieve reduction of a cell area of the memorycell. Besides, if this embodiment is applied to the 1T1C cell structuredescribed in the sixth embodiment, reduction in the cell area can befurther achieved As described above, the inventions made by presentinventors has been concretely described in accordance with theembodiments. Needless to say, the present invention is not be limited tothe above-stated embodiments and various changes and modifications canbe made without departing from the gist thereof.

[0174] In the embodiments stated above, in particular, the p-channeltype MISFET is formed on the n-type well 4 serving as the peripheralcircuit region. Alternatively, an n-channel type MISFET may be formed byforming a p-type well on the peripheral circuit region.

[0175] In the embodiments stated above, the laminating film consistingof the Ti film and the Pt film is used as the upper electrode of thecapacitor C and the Pt film is used as the lower electrode thereof. But,the present invention is not limited thereto. Alternatively, theseelectrodes may be made of a single layer film or a laminating layer,wherein the single layer film contains a platinum metal such as Pt, Ir,IrO₂, Ru, RuO₂ or the like, or an oxide thereof, or a double oxidethereof as a main component, and wherein the laminating layer isconstituted by two or more than conductive films selected from these.

[0176] Moreover, in the above-mentioned embodiments, although the PZTfilm is used as the ferroelectric film for the capacitive insulatingfilm, the present invention is not limited thereto and may use, forexample, a dielectric film which contains Pb included in PLZT(Pb_(1-x)La_(x)(Zr_(y)Ti₂)O₃) or the like and which has one belonging ina range between a high-dielectric-constant substance and a ferroelectricsubstance, as a main component.

[0177] Of inventions disclosed by the present application, advantagesobtained by representative ones will be briefly described as follows.

[0178] According to the present invention, the first and secondshielding films are formed on the upper portion of the upper electrodeof the capacitor or on the lower portion of the lower electrode.Therefore, it is possible to prevent H₂ or H₂O from entering the upperor lower portions of the capacitor and prevent characteristics of thehigh-dielectric-constant material or ferroelectric material (capacitiveinsulating film) from being degraded in the capacitor. In addition, thefirst and second shielding films can reduce diffusion of a component,e.g., lead included in the capacitive insulating film. And, if the leadcomposition ratio of each of the first and second shielding films is sethigher than that of the capacitive insulating film, then Pb diffusedfrom the inside of the capacitive insulating film can be compensated byPb included in the first and second shielding films, so that it ispossible to prevent the characteristics of the capacitive insulatingfilm from being degraded. As a result, the characteristics of the FeRAMmemory cell can be improved.

[0179] Further, according to the present invention, the barrier layerprovided in the interlayer insulating film can prevent H₂ or H₂O fromentering the upper portion of the capacitor and prevent thecharacteristics of the capacitive insulating film from being degraded inthe capacitor. As a result, the characteristics of the FeRAM memory cellcan be improved.

[0180] Moreover, according to the present invention, it is possible tomanufacture a semiconductor integrated circuit device capable ofpreventing the characteristics of the capacitive insulating film frombeing degraded in the capacitor.

1-12 (Cancelled)
 13. A method of manufacturing a semiconductorintegrated circuit device including a memory cell constituted by aMISFET and a capacitor, comprising steps of: forming the MISFET on asemiconductor substrate; forming an insulating film on said MISFET;depositing a first shielding film on said insulating film; depositing,on an upper surface of said first shielding film, a first conductivefilm, a capacitive insulating film comprised of ahigh-dielectric-constant material, and a second conductive film;patterning said second conductive film and said capacitive insulatingfilm exclusive of said first shielding film; and thereby forming, onsaid first shielding film, a capacitor constituted by a lower electrodecomprised of said first conductive film, said capacitive insulatingfilm, and an upper electrode comprised of said second conductive film;and forming a second shielding film covering sidewalls of said upperelectrode and said capacitor and being comprised of an insulating filmcontacting with an upper surface of said first shielding film, whereinsaid capacitor is disposed on said MISFET through said insulating film,said capacitor is covered with said first and second shielding films, aplug is formed so that a conductive film is embedded into a firstcontact hole formed by removing said insulating film and said firstshielding film on a source or drain region of said MISFET, said plugbeing connected to said lower electrode, a second contact hole is formedin said insulating film disposed on the other of the source or drainregion of said MISFET, and the other of the source or drain region ofsaid MISFET is connected through said second contact hole to a wiringformed on an upper portion of said insulating film.
 14. The method ofmanufacturing a semiconductor integrated circuit device according toclaim 13, wherein said first shielding film is formed so as to cover aforming region of said MISFET, and said second contact hole is formed insaid first shielding film.
 15. The method of manufacturing asemiconductor integrated circuit device according to claim 14, whereinsaid second shielding film is formed so as to cover a formation regionof said MISFET, and said second contact hole is formed in said secondshielding film.
 16. The method of manufacturing a semiconductorintegrated circuit device according to claim 14, wherein said firstshielding film is comprised of an insulating film.
 17. The method ofmanufacturing a semiconductor integrated circuit device according toclaim 13, wherein said step of forming the insulating film includes astep of annealing in a hydrogen atmosphere.
 18. A method ofmanufacturing a semiconductor integrated circuit device including amemory constituted by a MISFET and a capacitor, comprising steps of:forming a MISFET on a semiconductor device; forming an insulating filmon said MISFET; depositing a first shielding film on said insulatingfilm; depositing a first conductive film, a capacitive insulating filmcomprised of a ferroelectric material, and a second conductive film onsaid first shielding film; patterning said second conductive film andsaid capacitive insulating film exclusive of said first shielding film;and thereby forming, on said first shielding film, a capacitorconstituted by a lower electrode comprised of said first conductivefilm, said capacitive insulating film, and an upper electrode comprisedof the second conductive film; and forming a second shielding filmcomprised of an insulating film so as to cover sidewalls of said upperelectrode and said capacitor and contact with said first shielding film,wherein said capacitor is disposed on said MISFET through saidinsulating film, said capacitor is covered with said first and secondshielding films, said first shielding film is formed so as to cover aformation MISFET forming region, a plug is formed so that a conductivefilm is embedded in a first contact hole formed by removing saidinsulating film and said first shielding film disposed on a source ordrain region of said MISFET, said plug being connected to said lowerelectrode, a second contact hole is formed in said insulating filmdisposed on the other of the source or drain region of said MISFET, andthe other of the source or drain region of said MISFET is connected to awiring through said second contact hole.
 19. The method of manufacturinga semiconductor integrated circuit device according to claim 18, whereinsaid second shielding film is formed so as to cover the said MISFETforming region, said second contact hole is formed in said secondshielding film, and said first shielding film is comprised of aninsulating film.
 20. The method of manufacturing a semiconductorintegrated circuit device according to claim 18, wherein said wiring isformed on an upper portion of said insulating film.